1. Field of the Invention
This invention relates to a data holding apparatus that is capable of a high speed response and that does not require a use of a power source to hold data.
2. Description of the Related Art
SRAM (Static Random Access Memory) using MOSFET type transistors is known as a data holding apparatus. FIG. 30 is a circuit diagram of an example of a memory cell comprising a conventional SRAM. A memory cell MC is equipped with a pair of memory transistors MT1 and MT2 and a pair of resistors R1 and R2. Additionally, the memory cell MC is connected to a pair of select transistors ST1 and ST2 (in combination defined as a "a select transistor pair STP") by a pair of bit lines BL and BLB1 (in combination defined as a "bit line pair BLP"). The select transistor pair STP is connected to word lines WL. A number of such memory cells are placed in an array in a SRAM.
To write data in the memory cell MC of a SRAM, a pair of electric potentials that corresponds to data to be written is applied to the bit line pair BLP. To write Data "0", for example, a low electric potential "L" is applied to the bit line BL while a high electric potential "H" is applied to the bit line BLB. Next, the "H" electric potential is applied to word lines WL to turn ON the select transistor pair STP. This results in the memory transistor MT1 to go ON and the memory transistor MT2 to go OFF. Now, Data "0" is written in the memory cell MC. To write Data "1" in the memory cell MC, the high electric potential "H" is applied to the bit line BL and the low electric potential "L" is applied to the bit line BLB.
Subsequently changing the electric potential of the word lines WL to "L" turns the select transistor pair STP OFF and the memory cell goes into a standby state. In the standby state, written data is retained in the memory cell MC because of its self-latching capability. To read data, the electric potential "H" is applied to the word lines WL to turn ON the select transistor pair STP and to detect the voltage that appears in the bit line pair BLP. The content of the data is thus read out.
However, the above described SRAM had several problems. Because a voltage had to be consistently applied to the circuit to hold data, a power source was constantly required even when no data was being written or read. Consequently, SRAM consumed and wasted an electric power. Moreover, there was an inconvenience that a stored data was lost whenever the power source failed for any reason including an accident.
One of the solutions to the above noted problems may be to use a non-volatile storage element EEPROM as a memory element. However, this is infeasible for a data holding apparatus that must respond at a high speed since EEPROM requires a long time to write data.